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CY62148DV30
4-Mb (512K x 8) MoBL Static RAM
Features
* Very high speed: 55 ns -- Wide voltage range: 2.20V - 3.60V * Pin-compatible with CY62148CV25, CY62148CV30 and CY62148CV33 * Ultra low active power -- Typical active current: 1.5 mA @ f = 1 MHz * * * * * -- Typical active current: 8 mA @ f = fmax(55-ns speed) Ultra low standby power Easy memory expansion with CE, and OE features Automatic power-down when deselected CMOS for optimum speed/power Packages offered: 36-ball BGA, 32-pin TSOPII and 32-pin SOIC
Functional Description[1]
The CY62148DV30 is a high-performance CMOS static RAMs organized as 512K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBL) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption. The device can be put into standby mode reducing power consumption when deselected (CE HIGH). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW).
Logic Block Diagram
Data in Drivers
I/O0 I/O1
A0 A1 A2 A3 A4 A5 A A6 7 A8 A9 A10 A11 A12
ROW DECODER
SENSE AMPS
I/O2 I/O3 I/O4 I/O5
512K x 8 ARRAY
CE WE OE
COLUMN DECODER
POWER DOWN
I/O6 I/O7
Note: 1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05341 Rev. *B
*
3901 North First Street
A13 A14 A15 A16 A17 A18
*
San Jose, CA 95134 * 408-943-2600 Revised February 10, 2004
CY62148DV30
Pin Configuration[2,3]
FBGA
Top View
32 TSOPII
Top View
A0 I/O4 I/O5 VSS VCC I/O6 I/O7 A9
A1 A2
NC WE DNU
A3 A4 A5
A6 A7
A8 I/O0 I/O1 Vcc Vss
A B C D E F G H
A18 OE A10 CE A11
A17 A16 A12 A15 A13
I/O2 I/O3 A14
A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O 5 I/O4 I/O3
32 SOIC
A
A
Top View
A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O 5 I/O4 I/O3
Notes: 2. NC pins are not connected on the die. 3. DNU pins have to be left floating or tied to Vss to ensure proper application.
Document #: 38-05341 Rev. *B
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CY62148DV30
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Applied............................................... 55C to +125C Supply Voltage to Ground Potential ........................................ -0.3V to VCC(MAX) + 0.3V DC Voltage Applied to Outputs in High-Z State[4,5] ......................... -0.3V to VCC(MAX) + 0.3V DC Input Voltage[4,5] ......................-0.3V to VCC(MAX) + 0.3V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA
Operating Range
Product CY62148DV30L CY62148DV30LL Power Dissipation Operating ICC (mA) Range Ambient Temperature VCC[6]
Industrial -40C to +85C 2.2V to 3.6V
Product Portfolio
VCC Range (V) Product CY62148DV30L CY62148DV30LL CY62148DV30L CY62148DV30LL Min. 2.2 2.2 2.2 2.2 Typ.[7] 3.0 3.0 3.0 3.0 Max. 3.6 3.6 3.6 3.6
Speed (ns) 55 55 70 70
f = 1 MHz Typ.[7] 1.5 1.5 Max. 3 3 3 3 8 8
f = fmax Typ.[7] Max. 15 10 15 10
Standby ISB2 (uA) Typ.[7] 2 2 Max. 12 8 12 8
Electrical Characteristics Over the Operating Range
CY62148DV30-55 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Test Conditions IOH = -0.1 mA IOH = -1.0 mA IOL = 0.1 mA IOL = 2.1 mA VCC = 2.20V VCC = 2.70V VCC = 2.20V VCC = 2.70V 1.8 2.2 -0.3 -0.3 -1 -1 L LL L LL ISB1 Automatic CE Power-down Current -- CMOS Inputs Automatic CE Power-down Current -- CMOS Inputs L CE > VCC-0.2V, VIN>VCC-0.2V, VIN<0.2V) LL f = fMAX (Address and Data Only), f = 0 (OE, and WE), VCC=3.60V CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V L LL 2 12 8 2 12 8 2 2 12 8 12 8 A 1.5 8 Min. Typ.[7] 2.0 2.4 0.4 0.4 VCC + 0.3V 1.8 VCC + 0.3V 2.2 0.6 0.8 +1 +1 15 10 3 1.5 -0.3 -0.3 -1 -1 8 Max. CY62148DV30-70 Min. Typ.[7] 2.0 2.4 0.4 0.4 Max. Unit V V V V
VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V
VCC + 0.3V V VCC + 0.3V V 0.6 0.8 +1 +1 15 10 3 V V A A mA mA mA mA A
Input Leakage Current GND < VI < VCC Output Leakage Current GND < VO < VCC, Output Disabled
VCC Operating Supply f = fMAX = 1/tRC VCC = VCCmax IOUT = 0 mA Current CMOS levels f = 1 MHz
ISB2
Notes: 4. VIL(min.) = -2.0V for pulse durations less than 20 ns. 5. VIH(max) = VCC+0.75V for pulse durations less than 20 ns. 6. Full device AC operation assumes a 100 s ramp time from 0 to Vcc(min) and 200 s wait time after Vcc stabilization. 7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C.
Document #: 38-05341 Rev. *B
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CY62148DV30
Capacitance for all packages[8]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ.) Max. 10 10 Unit pF pF
Thermal Resistance
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board BGA 72 8.86 TSOP II 75.13 8.95 SOIC 55 22 STSOP 105 13 Unit C/W C/W
AC Test Loads and Waveforms
R1 VCC OUTPUT 50 pF INCLUDING JIG AND SCOPE R2 VCC 10% GND
Rise Time: 1 V/ns
ALL INPUT PULSES 90% 90% 10%
Fall time: 1 V/ns
Equivalent to:
THEVENIN EQUIVALENT RTH VTH
OUTPUT
Parameters R1 R2 RTH VTH
2.50V 16667 15385 8000 1.20
3.0V 1103 1554 645 1.75
Unit V
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR tCDR[8] tR[9] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = 1.5V, CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V L LL 0 tRC Conditions Min. Typ.[7] Max. Unit 1.5 9 6 V A A ns ns
Data Retention Waveform
DATA RETENTION MODE VCC 1.5V tCDR CE
Notes: 8. Tested initially and after any design or process changes that may affect these parameters. 9. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s.
VDR > 1.5 V
1.5V tR
Document #: 38-05341 Rev. *B
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CY62148DV30
Switching Characteristics (Over the Operating Range)[10]
55 ns Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle[13] tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High Z[11, 12] WE HIGH to Low Z[11] 10 55 40 40 0 0 40 25 0 20 10 70 45 45 0 0 45 30 0 25 ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[11] OE HIGH to High Z[11,12] CE LOW to Low Z[11] CE HIGH to High Z[11, 12] 0 55 CE LOW to Power-up CE HIGH to Power-up 10 20 0 70 5 20 10 25 10 55 25 5 25 55 55 10 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 70 ns Min. Max. Unit
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[14, 15]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Notes: 10. Test Conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" section. 11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 12. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state. 13. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 14. Device is continuously selected. OE, CE = VIL. 15. WE is HIGH for read cycle.
Document #: 38-05341 Rev. *B
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CY62148DV30
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled) [15, 16]
ADDRESS CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50%
[17, 19]
tRC
tHZOE tHZCE DATA VALID tPD
HIGH IMPEDANCE
DATA OUT
ICC 50% ISB
Write Cycle No. 1 (WE Controlled)
tWC ADDRESS tSCE CE tAW WE tSA tPWE tHA
OE tSD DATA I/O NOTE 18 tHZOE
Notes: 16. Address valid prior to or coincident with CE transition LOW. 17. Data I/O is high impedance if OE = VIH. 18. During this period, the I/Os are in output state and input signals should not be applied. 19. If CE goes HIGH simultaneously with WE HIGH, the output remains in high-impedance state.
tHD
DATAIN VALID
Document #: 38-05341 Rev. *B
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CY62148DV30
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[17, 19]
tWC ADDRESS tSCE CE tSA tAW tPWE WE tHA
OE tSD DATA I/O DATAIN VALID
[19]
tHD
Write Cycle No. 3 (WE Controlled, OE LOW)
ADDRESS
tWC
tSCE
CE
tAW tHA tPWE
WE
tSA
tSD
tHD
DATA I/O
NOTE 18
tHZWE
DATAIN VALID tLZWE
Truth Table
CE H L L L WE X H H L OE X L H X High Z Data Out (I/O0-I/O7) High Z Data in (I/O0-I/O7) Inputs/Outputs Read Output Disabled Write Mode Deselect/Power-down Power Standby (ISB) Active (ICC) Active (Icc) Active (Icc)
Ordering Information
Speed (ns) 55 55 55 55 Ordering Code CY62148DV30L-55BVI CY62148DV30LL-55BVI CY62148DV30L-55BVXI CY62148DV30LL-55BVXI CY62148DV30L-55ZSXI CY62148DV30LL-55ZSXI CY62148DV30L-55SXI CY62148DV30LL-55SXI Document #: 38-05341 Rev. *B Page 7 of 11 S-32 32-pin SOIC Pb-free Industrial ZS-32 32-pin TSOP II Pb-free Industrial BV36A 36-ball Very Fine Pitch BGA (6 mm x 8 mm x 1 mm) Pb-free Industrial Package Name BV36A Package Type 36-ball Very Fine Pitch BGA (6 mm x 8 mm x 1 mm) Operating Range Industrial
CY62148DV30
Ordering Information (continued)
Speed (ns) 70 70 70 70 Ordering Code CY62148DV30L-70BVI CY62148DV30LL-70BVI CY62148DV30L-70BVXI CY62148DV30LL-70BVXI CY62148DV30L-70ZSXI CY62148DV30LL-70ZSXI CY62148DV30L-70SXI CY62148DV30LL-70SXI S-32 32-pin SOIC Pb-free Industrial ZS-32 32-pin TSOP II Pb-free Industrial BV36A 36-ball Very Fine Pitch BGA (6 mm x 8 mm x 1 mm) Pb-free Industrial Package Name BV36A Package Type 36-ball Very Fine Pitch BGA (6 mm x 8 mm x 1 mm) Operating Range Industrial
Package Diagrams
36-Lead FBGA (6 x 8 x 1 mm) BV36A
51-85149-*B
Document #: 38-05341 Rev. *B
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CY62148DV30
Package Diagrams (continued)
32-Lead TSOP II ZS32
51-85095-**
Document #: 38-05341 Rev. *B
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CY62148DV30
Package Diagrams (continued)
32-Lead (450 MIL) Molded SOIC S34
16 1
0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430]
17
32
0.793[20.142] 0.817[20.751]
0.006[0.152] 0.012[0.304] 0.118[2.997] MAX. 0.004[0.102] 0.047[1.193] 0.063[1.600]
0.101[2.565] 0.111[2.819]
0.050[1.270] BSC.
0.004[0.102] MIN. 0.014[0.355] 0.020[0.508]
0.023[0.584] 0.039[0.990]
SEATING PLANE
51-85081-*B
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05341 Rev. *B
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(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62148DV30
Document History Page
Document Title:CY62148DV30 4-Mb (512K x 8) MoBL Static RAM Document Number: 38-05341 REV. ** *A *B ECN NO. 127480 131041 222180 Issue Date 06/17/03 01/23/04 See ECN Orig. of Change HRT CBD AJU Created new data sheet Change from Advance to Preliminary Change from Preliminary to Final Added 70 ns speed bin Modified footnote #6 and #12 Removed MAX value for VDR on "Data Retention Characteristics" table Modified input and output capacitance values Added Pb-free ordering information Removed 32-pin STSOP package Description of Change
Document #: 38-05341 Rev. *B
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